CMOS-compatible strain engineering for monolayer semiconductor transistors | Nature Electronics

Nature Electronics volume 7, pages 885–891 (2024)Cite this article

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Strain engineering has played a key role in modern silicon electronics, having been introduced as a mobility booster in the 1990s and commercialized in the early 2000s. Achieving similar advances with two-dimensional (2D) semiconductors in a complementary metal–oxide–semiconductor (CMOS)-compatible manner could improve the industrial viability of 2D material transistors. Here, we show that silicon nitride capping layers can impart strain to monolayer molybdenum disulfide (MoS2) transistors on conventional silicon substrates, improving their performance with a CMOS-compatible approach, at a low thermal budget of 350 °C. Strained back-gated and dual-gated MoS2 transistors exhibit median increases in on-state current of up to 60% and 45%, respectively. The greatest improvements are found when reducing both transistor channels and contacts from micrometre-scale to 200 nm, reaching saturation currents of 488 µA µm−1 in devices with just 400 nm contact pitch. Simulations show that the performance enhancement is mainly due to tensile strain lowering the contact Schottky barriers, and that further reducing device dimensions, including contacts, could lead to additional increases in strain and performance.

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The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

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This work was performed in part at the Stanford Nanofabrication Facility and the Stanford Nano Shared Facilities, which are supported by the National Science Foundation (Award ECCS-2026822). This study was partly supported by the Stanford SystemX Alliance, the Samsung Global Research Outreach programme and Intel Corporation. M.J. and K.N. acknowledge support from a Stanford graduate fellowship. C.K. and E.P. acknowledge partial support from the SUPREME JUMP 2.0 Center, a Semiconductor Research Corporation programme sponsored by the Defense Advanced Research Projects Agency. J.A.Y. acknowledges support from a National Science Foundation graduate research fellowship. We wish to thank J. P. McVittie and M. Xue for fruitful discussions.

Department of Electrical Engineering, Stanford University, Stanford, CA, USA

Marc Jaikissoon, Çağıl Köroğlu, Jerry A. Yang, Kathryn Neilson, Krishna C. Saraswat & Eric Pop

Department of Materials Science & Engineering, Stanford University, Stanford, CA, USA

Krishna C. Saraswat & Eric Pop

Department of Applied Physics, Stanford University, Stanford, CA, USA

Eric Pop

Precourt Institute for Energy, Stanford University, Stanford, CA, USA

Eric Pop

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M.J., E.P. and K.C.S. conceived the work. M.J. performed the MoS2 synthesis, SiNx recipe development, device fabrication, optical characterization, electrical measurements and scanning electron microscopy. C.K. contributed all the numerical simulations of the strain profiles. K.N. performed the WSe2 synthesis and atomic layer deposition with J.A.Y. M.J. analysed all the data and wrote the manuscript with help from C.K. and E.P. All authors have given approval to the final version of the manuscript.

Correspondence to Eric Pop.

The authors declare no competing interests.

Nature Electronics thanks Yuan Liu, Xiaoyan Liu and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Supplementary Figs. 1–13, accompanying discussion and Table 1.

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Jaikissoon, M., Köroğlu, Ç., Yang, J.A. et al. CMOS-compatible strain engineering for monolayer semiconductor transistors. Nat Electron 7, 885–891 (2024). https://doi.org/10.1038/s41928-024-01244-7

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Received: 29 October 2023

Accepted: 15 August 2024

Published: 23 October 2024

Issue Date: October 2024

DOI: https://doi.org/10.1038/s41928-024-01244-7

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